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1 e92929d01 sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. absolute maximum ratings (ta=25 c) ? supply voltage av dd , dv dd 7v ? input voltage (all pins) v in v dd +0.5 to v ss C0.5 v ? output current (for each channel) i out 0 to 30 ma ? storage temperature tstg C55 to +150 c recommended operating conditions ? supply voltage av dd , av ss 4.75 to 5.25 v dv dd , dv ss 4.75 to 5.25 v ? reference input voltage v ref 1.8 to 2.0 v ? clock pulse width t pw1, t pw0 9 ns (min.) to 1.1 s (max.) ? operating temperature topr C20 to +75 c description the CXD2308Q is a 10-bit high-speed d/a converter for video band, featuring rgb 3-channel i/o. this is ideal for use in high-definition tvs and high-resolution displays. features ? resolution 10-bit ? maximum conversion speed 50msps ? rgb 3-channel i/o ? differential linearity error 0.5lsb ? low power consumption 500 mw (typ.) ? single +5 v power supply ? low glitch ? stand-by function structure silicon gate cmos ic 10-bit 50msps rgb 3-channel d/a converter 64 pin qfp (plastic) CXD2308Q
2 CXD2308Q block diagram 4 l s b ' s c u r r e n t c e l l s 6 m s b ' s c u r r e n t c e l l s c l o c k g e n e r a t o r c u r r e n t c e l l s ( f o r f u l l s c a l e ) 4 l s b ' s c u r r e n t c e l l s 6 m s b ' s c u r r e n t c e l l s c l o c k g e n e r a t o r c u r r e n t c e l l s ( f o r f u l l s c a l e ) 4 l s b ' s c u r r e n t c e l l s 6 m s b ' s c u r r e n t c e l l s c l o c k g e n e r a t o r c u r r e n t c e l l s ( f o r f u l l s c a l e ) b i a s v o l t a g e g e n e r a t o r d e c o d e r l a t c h e s d e c o d e r d e c o d e r l a t c h e s d e c o d e r d e c o d e r l a t c h e s d e c o d e r r o g 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 3 6 4 6 1 6 2 3 1 3 2 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 1 ( l s b ) r 0 r 1 r 2 r 3 r 4 r 5 r 6 r 7 r 8 ( m s b ) r 9 ( l s b ) g 0 g 1 g 2 g 3 g 4 g 5 g 6 g 7 g 8 ( m s b ) g 9 ( l s b ) b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b l k c e d v d d a v d d a v d d v g r r o r o r c k r o r v r r i r r a v d d a v d d v g g g o g o g c k r o g v r g i r g a v d d a v d d v g b b o b o b c k r o b v r b i r b v b a v s s a v s s d v s s ( m s b ) b 9
3 CXD2308Q pin configuration 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 3 6 4 6 1 6 2 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 r o r o a v d d a v d d g o g o a v d d a v d d b o b o a v d d a v d d d v d d c e b l k b 9 ( m s b ) b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ( l s b ) g 9 ( m s b ) a v s s v g b r o b v g g r o g v g r r o r v r b v r g v r r i r b i r g i r r a v s s v b d v s s b c k g c k r c k ( l s b ) r 0 r 1 r 2 r 3 r 4 r 5 r 6 r 7 r 8 ( m s b ) r 9 ( l s b ) g 0 g 1 g 2 g 3 g 4 g 5 g 6 g 7 g 8 pin description and equivalent circuit 1 to 10 11 to 20 21 to 30 31 32 33 34 35 36 r0 to r9 g0 to g9 b0 to b9 blk ce rck gck bck dv ss i pin no. symbol i/o equivalent circuit description 3 5 1 d v d d d v s s t o digital input. r0 (lsb) to r9 (msb) g0 (lsb) to g9 (msb) b0 (lsb) to b9 (msb) blanking input. this is synchronized with the clock input signal for each channel. no signal for high (0 v output). output generated for low. chip enable input. this is not synchronized with the clock input signal. no signal at for high (0 v output) to minimize power consumption. clock inputs. digital ground.
4 CXD2308Q 37 38, 51 45 47 49 46 48 50 39 40 41 42 43 44 vb av ss ror rog rob vgr vgg vgb irr irg irb vrr vrg vrb o i o i pin no. symbol i/o equivalent circuit description d v d d d v s s d v d d 3 7 4 2 4 4 4 5 4 6 4 9 5 0 a v s s 3 9 4 1 4 0 a v s s 4 8 a v d d a v d d a v s s a v d d 4 7 a v s s a v d d 4 3 connect to dv ss with a capacitor of approximately 0.1 f. analog grounds. connect to vgr, vgg, and vgb with the control method of output amplitude. see application circuit. connect a capacitor of approximately 0.1 f. reference current output. connect to av ss with a resistance of 1.2 k . reference voltage input. set output full-scale value (2.0 v).
5 CXD2308Q 52 56 60 53 57 61 54, 55, 58, 59, 62, 63 64 ro go bo ro go bo av dd dv dd pin no. symbol i/o equivalent circuit description 5 2 5 3 6 0 6 1 a v d d a v s s a v d d a v s s 5 6 5 7 current output. output can be retrieved by connecting a resistance of 75 to av ss . reverse current output. normally connected to av ss . analog v dd . digital v dd . a a a a a a a a a a a a a a a a a a t p w 1 t p w 0 t s t h t s t h t s t h t p d t p d t p d c l k d a t a d / a o u t 1 0 0 % 5 0 % 0 % 1 . 5 v i/o correspondence table (output full-scale voltage: 2.00 v) input code output voltage msb lsb 1 1 1 1 1 1 1 1 1 1 : 1 0 0 0 0 0 0 0 0 0 : 0 0 0 0 0 0 0 0 0 0 2.0 v 1.0 v 0 v description of operation timing chart
6 CXD2308Q electrical characteristics (f clk =50 mhz, av dd =dv dd =5 v, r out =75 , v ref =2.0 v, ta=25 c) item resolution conversion speed integral non-linearity error differential non-linearity error precision guaranteed output voltage range output full-scale voltage output full-scale ratio * 1 output full-scale current output offset voltage glitch energy crosstalk supply current analog input resistance input capacitance output capacitance digital input voltage digital input current setup time hold time propagation delay time ce enable time * 2 ce disable time * 2 symbol n f clk e l e d v oc v fs f sr i fs v os ge ct i dd i stb r in c i c o v ih v il i ih i il t s t h t pd t e t d measurement conditions av dd =dv dd =4.75 to 5.25 v ta=C20 to +75 c endpoint for the same gain (see the application circuit) when data 0000000000 input when 1 khz sine wave input ce= l ce= h vgr, vgg, vgb, vrr, vrg, vrb ro, go, bo av dd =dv dd =4.75 to 5.25 v ta=C20 to +75 c av dd =dv dd =4.75 to 5.25 v ta=C20 to +75 c ce=h ? l ce=l ? h min. 0.5 C2.0 C0.5 1.8 1.8 0 1 2.15 C5 7 3 typ. 10 1.9 1.9 1.5 27 50 54 100 50 10 1 1 max. 50 2.0 0.5 2.0 2.0 3 30 1 110 1 9 0.85 5 2 2 unit bit msps lsb lsb v v % ma mv pv?s db ma m pf pf v a ns ns ns ms ms full-scale voltage for each channel * 1 output full-scale ratio = full-scale voltage average value for each channel C1 100 (%) * 2 when the external capacitors for the vgr, vgg and vgb pins are 0.1 f. electrical characteristics measurement circuit analog input resistance measurement circuit digital input current c x d 2 3 0 8 q + 5 . 2 5 v a v d d , d v d d a v s s , d v s s v a }
7 CXD2308Q v g r t o v g b 4 6 , 4 8 , 5 0 r o r t o r o b 4 5 , 4 7 , 4 9 v r r t o v r b 4 2 t o 4 4 i r r t o i r b 3 9 t o 4 1 r c k 1 0 b i t c o u n t e r w i t h l a t c h c l k 5 0 m h z s q u a r e w a v e g c k b c k 0 . 1 d v s s 7 5 a v s s 7 5 a v s s 7 5 a v s s 1 . 2 k 2 v 0 . 1 a v d d o s c i l l o s c o p e b l k c e v b r o r o g o b o b o r 0 t o r 9 1 t o 1 0 g 0 t o g 9 1 1 t o 2 0 b 0 t o b 9 2 1 t o 3 0 3 5 3 4 3 3 5 2 5 3 5 6 5 7 6 0 6 1 3 7 3 1 3 2 d e l a y c o n t r o l l e r d e l a y c o n t r o l l e r g o maximum conversion speed measurement circuit v g r t o v g b 4 6 , 4 8 , 5 0 r o r t o r o b 4 5 , 4 7 , 4 9 v r r t o v r b 4 2 t o 4 4 i r r t o i r b 3 9 t o 4 1 r c k 1 0 b i t c o u n t e r w i t h l a t c h c l k 5 0 m h z s q u a r e w a v e g c k b c k 0 . 1 d v s s 7 5 a v s s 7 5 a v s s 7 5 a v s s 1 . 2 k 2 v 0 . 1 a v d d o s c i l l o s c o p e b l k c e v b r o r o g o b o b o r 0 t o r 9 1 t o 1 0 g 0 t o g 9 1 1 t o 2 0 b 0 t o b 9 2 1 t o 3 0 3 5 3 4 3 3 5 2 5 3 5 6 5 7 6 0 6 1 3 7 3 1 3 2 g o setup time hold time measurement circuit glitch energy } cross talk measurement circuit v g r t o v g b 4 6 , 4 8 , 5 0 r o r t o r o b 4 5 , 4 7 , 4 9 v r r t o v r b 4 2 t o 4 4 i r r t o i r b 3 9 t o 4 1 r c k c l k 5 0 m h z s q u a r e w a v e g c k b c k 0 . 1 d v s s 7 5 a v s s 7 5 a v s s 7 5 a v s s 1 . 2 k 2 v 0 . 1 a v d d b l k c e v b r o r o g o b o b o r 0 t o r 9 1 t o 1 0 g 0 t o g 9 1 1 t o 2 0 b 0 t o b 9 2 1 t o 3 0 3 5 3 4 3 3 5 2 5 3 5 6 5 7 6 0 6 1 3 7 3 1 3 2 d i g i t a l w a v e f o r m g e n e r a t o r a l l 1 g o s p e c t r u m a n a l y z e r
8 CXD2308Q v g r t o v g b 4 6 , 4 8 , 5 0 r o r t o r o b 4 5 , 4 7 , 4 9 v r r t o v r b 4 2 t o 4 4 i r r t o i r b 3 9 t o 4 1 r c k c l k 5 0 m h z s q u a r e w a v e g c k b c k 0 . 1 d v s s 7 5 a v s s 7 5 a v s s 7 5 a v s s 1 . 2 k 2 v 0 . 1 a v d d b l k c e v b r o r o g o b o b o r 0 t o r 9 1 t o 1 0 g 0 t o g 9 1 1 t o 2 0 b 0 t o b 9 2 1 t o 3 0 3 5 3 4 3 3 5 2 5 3 5 6 5 7 6 0 6 1 3 7 3 1 3 2 g o f r e q u e n c y d e m u l t i p l i e r o s c i l l o s c o p e dc characteristics measurement circuit v g r t o v g b 4 6 , 4 8 , 5 0 r o r t o r o b 4 5 , 4 7 , 4 9 v r r t o v r b 4 2 t o 4 4 i r r t o i r b 3 9 t o 4 1 r c k c l k 5 0 m h z s q u a r e w a v e g c k b c k 0 . 1 d v s s 7 5 a v s s 7 5 a v s s 7 5 a v s s 1 . 2 k 2 v 0 . 1 a v d d b l k c e v b r o r o g o b o b o r 0 t o r 9 1 t o 1 0 g 0 t o g 9 1 1 t o 2 0 b 0 t o b 9 2 1 t o 3 0 3 5 3 4 3 3 5 2 5 3 5 6 5 7 6 0 6 1 3 7 3 1 3 2 g o c o n t r o l l e r d v m propagation delay time measurement circuit
9 CXD2308Q application circuit (gain equal) a v d d a v s s d v s s r c h a n n e l i n p u t g c h a n n e l i n p u t 0 . 1 f 1 . 2 k w n c n c 1 k w n c n c 0 . 1 f 7 5 w 7 5 w 7 5 w 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 3 6 4 6 1 6 2 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 c l o c k i n p u t b c h a n n e l i n p u t d v d d r o u t g o u t b o u t a v d d a v s s r c h a n n e l i n p u t g c h a n n e l i n p u t 0 . 1 f 1 . 2 k w 1 k w 0 . 1 f 7 5 w 7 5 w 7 5 w 0 . 1 f 0 . 1 f 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 3 6 4 6 1 6 2 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 b c h a n n e l i n p u t c l o c k i n p u t d v d d d v s s r o u t g o u t b o u t (gain independently) application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
10 CXD2308Q notes on operation ? how to select the output resistance the CXD2308Q is a d/a converter of the current output type. to obtain the output voltage connect the resistance to ro, go and bo pin. for specifications we have: output full scale voltage v fs =1.8 to 2.0 [v] output full scale current i fs =less than 30 [ma] calculate the output resistance value from the relation of v fs =i fs r out . also, 16 times resistance of the output resistance is connected to reference current pin irr, irg and irb. in some cases, however, this turns out to be a value that does not actually exist. in such a case a value close to it can be used as a substitute. here please note that v fs becomes v fs =v ref 16r out /r ir . v ref is the voltage set at the vrr, vrg and vrb pins and r out is the resistance connected to ro, go and bo while r ir is connected to irr, irg and irb. increasing the resistance value can curb power consumption. on the other hand glitch energy and data settling time will inversely increase. set the most suitable value according to the desired application. ? phase relation between data and clock to obtain the expected performance as a d/a converter, it is necessary to set properly the phase relation between data and clock applied from the exterior. be sure to satisfy the provisions of the setup time (t s ) and hold time (t h ) as stipulated in the electrical characteristics. ? power supply and ground to reduce noise effects separate analog and digital systems in the device periphery. for power supply pins, both digital and analog, bypass respective grounds by using a ceramic capacitor of about 0.1 f, as close as possible to the pin. ? latch up analog and digital power supply have to be common at the pcb power supply source. this is to prevent latch up due to voltage difference between av dd and dv dd pins when power supply is turned on. ? ro, go and bo pins the ro, go and bo pins are the inverted current output pins described in the pin description. the sums shown below become the constant value for any input data. a) the sum of the currents output from ro and ro b) the sum of the currents output from go and go c) the sum of the currents output from bo and bo however, the performances such as the linearity error of the inverted current output pin output current is not guaranteed. ? output full-scale voltage for the applications using the rgb signal, the color balance may be broken up when the no-adjusted output full-scale voltage of ro, go and bo are used.
11 CXD2308Q c a v s s d v s s a v s s d v s s a v d d d v d d c x d 2 3 0 8 q c d v d d d i g i t a l i c + 5 v latch up prevention the CXD2308Q is a cmos ic which requires latch up precautions. latch up is mainly generated by the lag in the voltage rising time of av dd and dv dd , when power supply is on. 1. correct usage a. when analog and digital supplies are from different sources b. when analog and digital supplies are from a common source (i) (ii) a v d d + 5 v a v s s d v s s a v s s d v s s a v d d d v d d c x d 2 3 0 8 q c d v d d d i g i t a l i c c + 5 v a v s s d v s s a v s s d v s s a v d d d v d d c x d 2 3 0 8 q c d v d d d i g i t a l i c c + 5 v
12 CXD2308Q 2. example when latch up easily occurs a. when analog and digital supplies are from different sources b. when analog and digital supplies are from common source (i) (ii) a v d d + 5 v a v s s d v s s a v s s d v s s a v d d d v d d c x d 2 3 0 8 q d v d d d i g i t a l i c c + 5 v c c a v s s d v s s a v s s d v s s a v d d d v d d c x d 2 3 0 8 q d v d d d i g i t a l i c a v d d c + 5 v + 5 v a v s s d v s s a v s s d v s s a v d d d v d d c x d 2 3 0 8 q d v d d d i g i t a l i c a v d d c
13 CXD2308Q example of representative characteristics o u t p u t f r e q u e n c y v s . c r o s s t a l k o u t p u t f r e q u e n c y f o [ h z ] 1 0 0 k 1 m 1 0 m c r o s s t a l k c t [ d b ] 8 0 7 0 6 0 5 0 4 0 a v d d = d v d d = 5 . 0 v f c l k = 5 0 m s p s v r e f = 2 . 0 v t a = 2 5 c r o u t = 7 5 w r i r = 1 . 2 k w a m b i e n t t e m p e r a t u r e v s . f u l l - s c a l e v o l t a g e f u l l - s c a l e v o l t a g e v f s [ v ] 1 . 9 1 . 8 2 0 0 2 5 5 0 7 0 a m b i e n t t e m p e r a t u r e t a [ c ] a m b i e n t t e m p e r a t u r e v s . c u r r e n t c o n s u m p t i o n a m b i e n t t e m p e r a t u r e t a [ c ] c u r r e n t c o n s u m p t i o n i d d [ m a ] 1 0 0 2 0 0 2 5 5 0 7 5 1 1 0 a v d d = d v d d = 5 . 0 v f c l k = 5 0 m s p s v r e f = 2 . 0 v r o u t = 7 5 r i r = 1 . 2 k w w a v d d = d v d d = 5 . 0 v f c l k = 5 0 m s p s v r e f = 2 . 0 v r o u t = 7 5 r i r = 1 . 2 k w w
package outline unit : mm CXD2308Q 14 s o n y c o d e e i a j c o d e j e d e c c o d e 2 3 . 9 0 . 4 2 0 . 0 0 . 1 0 . 4 0 . 1 + 0 . 1 5 1 4 . 0 0 . 1 1 1 9 2 0 3 2 3 3 5 1 5 2 6 4 0 . 1 5 0 . 0 5 + 0 . 1 2 . 7 5 0 . 1 5 1 6 . 3 0 . 1 0 . 0 5 + 0 . 2 0 . 8 0 . 2 m 0 . 2 0 . 1 5 + 0 . 4 1 7 . 9 0 . 4 + 0 . 4 + 0 . 3 5 6 4 p i n q f p ( p l a s t i c ) q f p - 6 4 p - l 0 1 q f p 0 6 4 - p - 1 4 2 0 p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r / p a l l a d i u m 4 2 / c o p p e r a l l o y p a c k a g e s t r u c t u r e p l a t i n g 1 . 5 g 1 . 0 0 t o 1 0

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